The present invention relates to a semiconductor device having a plurality of output bits and, more particularly, to a semiconductor device with reduced peak current.
Generally, in microcomputers, the data processing speed is one of the important factors. In recent years, more speed up is required for the operations of central processing units (CPU) or memories.
In the microcomputer systems, the output of the semiconductor memory is coupled with the data bus. A capacitance present in the data bus is very large and in the semiconductor memory it reaches about 150 pF. In designing the semiconductor memories, time taken from the address input to the data output is determined by considering the capacitance of the data bus. That time is selected shorter as the operating speed of the semiconductor memory increases.
The predominantly used microcomputers are of 8 bit type. In the description to follow, the semiconductor memory of 8 bits output will be used. Assume that the output signals of 8 bits from the memory simultaneously change their logical state from "0" to "1". Further, assume that the memory output signal rises from 0 V to 3 V for 20 nsec. Since each bit has a capacitance of 150 pF, 8 bits have 1200 pF (=150 pF.times.8) capacitance and such a large capacitance must be driven. The necessary current I for driving the large capacitance is given by I=CV/t=8.times.150.times.10.sup.-12 .times.3/20.times.10.sup.-9 =180 mA. In this example, 180 mA flows instantaneously. The ordinary operation current of the semiconductor memory is about 100 mA to 150 mA. For this reason, when such large current of 180 mA abruptly flows, noise is induced into the power source and the ground line, resulting in deterioration of the stable operation of the memory. In the RAM (random access memory), there is a danger that the data of the RAM are destroyed by the noise. An adverse effect of the induced noise on the peripheral integrated circuit must also be taken in account. Therefore, when the above memory is used, an additional consideration is required in designing the microcomputers.
The necessary current as mentioned above will be described referring to the semiconductor memory shown in FIG. 1. The semiconductor memory is comprised of a row decoder 10, a plurality of memory cell arrays 14.sub.1 to 14.sub.n connected through a row line 12 to the row decoder 10, a plurality of column select circuits 18.sub.1 to 18.sub.n connected through a column line 16 to the memory cell arrays 14.sub.1 to 14.sub.n, a column decoder 20 connected to the column select circuits 18.sub.1 to 18.sub.n, a plurality of sense amplifiers 22.sub.1 to 22.sub.n correspondingly connected to the column select circuits 18.sub.1 to 18.sub.n, and a plurality of output buffer circuits 24.sub.1 to 24.sub.n correspondingly connected to the sense amplifiers 22.sub.1 to 22.sub.n. The output terminals of the output buffer circuits 24.sub.1 to 24.sub.n are correspondingly connected to external output terminals, respectively.
In each of the memory cell arrays 14.sub.1 to 14.sub.n, memory cells are located at cross points of the row lines 12 and the column lines 16. A desired memory cell at the cross points is specified by one of the row lines driven by the row decoder 10 in response to a row address input signal and one column line selected respectively by the column select circuits 18.sub.1 to 18.sub.n driven by the column decoder 20 in response to a column address input signal. Through the consecutive memory cell specifying operations, data are read out bit by bit from the memory cell arrays 14.sub.1 to 14.sub.n. In this way, the data of 8 bits are sent to the external output terminals.
In the semiconductor memory, to minimize the chip size, the row lines are wired using polysilicon and the output lines of the column decoder 20 are wired using aluminum. Since polysilicon has normally 30 to 50 .OMEGA./.mu..sup.2, a voltage on the row line remote from the row decoder 10 has a time delay with respect to that on the line near the row decoder 10. When a memory cell of each of the memory cell arrays is selected depending on a change of the row address, the memory cell near the row decoder is selected faster selected than the remote one. Accordingly, times that the data are produced from the selected memories are different depending on the locations of the selected memory cells from the row decoder 10. Therefore, the data of 8 bits are not simultaneously produced from the output buffers 24.sub.1 to 24.sub.n and the above 180 mA never flows.
Let us consider a case where only the column address changes. The output lines from the column decoder 20 are made of aluminum, as previously stated, due to the pattern layout employed in their fabrication stage. Their resistance is about 0.OMEGA.. In selecting the column lines by the column select circuit, each of the column selects circuits select a single column line. The column line selections by the select circuits are performed simultaneously. Therefore, 8-bit data are simultaneously outputted from the selected memory cells. Then, the 180 mA current instantaneously flows at this time, possibly resulting in an erroneous operation. Thus, when the column addresses change to produce data, there is the highest possibility that noise is induced into the power source and the ground line.
In FIG. 2, illustrating the output buffers of CPU, the output buffers 28.sub.1 to 28.sub.n connected to an internal bus 26 produce data to an external bus 30 under control of a control signal S. When the control signal S is inputted to the output buffers 28.sub.1 to 28.sub.n concurrently and the buffers operate, a large instantaneous current flows to cause noise in the semiconductor device.
FIG. 3 illustrates another prior semiconductor memory with a plurality of bits. The column lines of memory cell arrays 14.sub.1 to 14.sub.n are simultaneously precharged by a column line precharge circuit 32, in synchronism with a precharge signal PC. The contents of the memory cell selected by the row decoder 10 appear on paired column lines Q.sub.1 and Q.sub.1 to Q.sub.n and Q.sub.n. A column decoder 20 drives column select circuits 18.sub.1 to 18.sub.n. Data on the column lines decoded by the column select circuits 18.sub.1 to 18.sub.n are sensed by sense amplifiers 22.sub.1 to 22.sub.n. The sensed values are outputted to output terminals through output buffers 24.sub.1 to 24.sub.n.
FIG. 4 shows yet another prior semiconductor memory with a plurality of output bits. The column lines of memory cell arrays 14.sub.1 to 14.sub.n are simultaneously precharged by column line precharge circuits 32.sub.1 to 32.sub.n in synchronism with a precharged signal PC. The data of the memory cell selected by the row decoder 10 appear on the column lines Q.sub.11 to Q.sub.nm. The data are sensed by corresponding sense amplifier circuits 22.sub.1 to 22.sub.n, respectively. The output signals from the sense amplifiers 22.sub.1 to 22.sub.n are selected by column select circuits 18.sub.1 to 18.sub.n and produced to output terminals 24.sub.1 to 24.sub.n, respectively.
In the prior semiconductor memories shown in FIGS. 3 and 4, a pulse width of the precharge signal PC is determined by detecting that the output signal from the row decoder 10 reaches the terminal E.sub.n of the row line 12 (FIG. 3). Since the row lines 12 are normally made of polysilicon, those have about 30 .OMEGA./.quadrature.. The row line 12 has a relatively large load capacitance since such lines are connected to the gates of the memory cell transistors. For this reason, there is a difference between a rise time of data at a node E.sub.o near the row decoder 10 and that at a node E.sub.n remote from the row decoder 10. To cope with this problem, the prior art precharges the column lines until the data on the row lines reach E.sub.n and the row lines 12 all have a "1" level. At an instant that the signal level on the row lines 12 becomes a "1" level, the precharge signal PC is stopped.
FIG. 5 shows an example of the precharge circuit.
In the semiconductor memory as mentioned above, at an instant that the precharge is stopped, the sense amplifiers 22.sub.1 to 22.sub.n start to operate. The output data from the sense amplifiers are transferred to the output buffer circuits 24.sub.1 to 24.sub.n of the data input/output circuit, respectively. In this way, the initial operation of the respective sense amplifiers and the outputs of data of the plurality of bits are performed concurrently. As a result, the instantaneous peak current is very large. This causes noise in the power source, like the FIG. 1 prior art. Additionally, the noise induced narrows an operating margin of the circuit in each memory. Since a large capacitance of about 150 pF is contained in the exterior circuit, as mentioned above, the instantaneous current due to the charge/discharge to and from the capacitor is considerably large.